HAL SPI constants migration

This section provides information about the HAL SPI constants migration .

HAL SPI master SS idleness constants

HAL1

HAL2 



#define SPI_MASTER_SS_IDLENESS_00CYCLE
#define SPI_MASTER_SS_IDLENESS_01CYCLE
#define SPI_MASTER_SS_IDLENESS_02CYCLE
#define SPI_MASTER_SS_IDLENESS_03CYCLE
#define SPI_MASTER_SS_IDLENESS_04CYCLE
#define SPI_MASTER_SS_IDLENESS_05CYCLE
#define SPI_MASTER_SS_IDLENESS_06CYCLE
#define SPI_MASTER_SS_IDLENESS_07CYCLE
#define SPI_MASTER_SS_IDLENESS_08CYCLE
#define SPI_MASTER_SS_IDLENESS_09CYCLE
#define SPI_MASTER_SS_IDLENESS_10CYCLE
#define SPI_MASTER_SS_IDLENESS_11CYCLE
#define SPI_MASTER_SS_IDLENESS_12CYCLE
#define SPI_MASTER_SS_IDLENESS_13CYCLE
#define SPI_MASTER_SS_IDLENESS_14CYCLE
#define SPI_MASTER_SS_IDLENESS_15CYCLE

typedef enum
{
  HAL_SPI_NSS_MSSI_DELAY_00CYCLE
  HAL_SPI_NSS_MSSI_DELAY_01CYCLE
  HAL_SPI_NSS_MSSI_DELAY_02CYCLE
  HAL_SPI_NSS_MSSI_DELAY_03CYCLE
  HAL_SPI_NSS_MSSI_DELAY_04CYCLE
  HAL_SPI_NSS_MSSI_DELAY_05CYCLE
  HAL_SPI_NSS_MSSI_DELAY_06CYCLE
  HAL_SPI_NSS_MSSI_DELAY_07CYCLE
  HAL_SPI_NSS_MSSI_DELAY_08CYCLE
  HAL_SPI_NSS_MSSI_DELAY_09CYCLE
  HAL_SPI_NSS_MSSI_DELAY_10CYCLE
  HAL_SPI_NSS_MSSI_DELAY_11CYCLE
  HAL_SPI_NSS_MSSI_DELAY_12CYCLE
  HAL_SPI_NSS_MSSI_DELAY_13CYCLE
  HAL_SPI_NSS_MSSI_DELAY_14CYCLE
  HAL_SPI_NSS_MSSI_DELAY_15CYCLE
} hal_spi_nss_mssi_delay_t;

Related concepts:

HAL SPI master inter-data idleness constants

HAL1

HAL2 



#define SPI_MASTER_INTERDATA_IDLENESS_00CYCLE
#define SPI_MASTER_INTERDATA_IDLENESS_01CYCLE
#define SPI_MASTER_INTERDATA_IDLENESS_02CYCLE
#define SPI_MASTER_INTERDATA_IDLENESS_03CYCLE
#define SPI_MASTER_INTERDATA_IDLENESS_04CYCLE
#define SPI_MASTER_INTERDATA_IDLENESS_05CYCLE
#define SPI_MASTER_INTERDATA_IDLENESS_06CYCLE
#define SPI_MASTER_INTERDATA_IDLENESS_07CYCLE
#define SPI_MASTER_INTERDATA_IDLENESS_08CYCLE
#define SPI_MASTER_INTERDATA_IDLENESS_09CYCLE
#define SPI_MASTER_INTERDATA_IDLENESS_10CYCLE
#define SPI_MASTER_INTERDATA_IDLENESS_11CYCLE
#define SPI_MASTER_INTERDATA_IDLENESS_12CYCLE
#define SPI_MASTER_INTERDATA_IDLENESS_13CYCLE
#define SPI_MASTER_INTERDATA_IDLENESS_14CYCLE
#define SPI_MASTER_INTERDATA_IDLENESS_15CYCLE

typedef enum
{
  HAL_SPI_MIDI_DELAY_00CYCLE
  HAL_SPI_MIDI_DELAY_01CYCLE
  HAL_SPI_MIDI_DELAY_02CYCLE
  HAL_SPI_MIDI_DELAY_03CYCLE
  HAL_SPI_MIDI_DELAY_04CYCLE
  HAL_SPI_MIDI_DELAY_05CYCLE
  HAL_SPI_MIDI_DELAY_06CYCLE
  HAL_SPI_MIDI_DELAY_07CYCLE
  HAL_SPI_MIDI_DELAY_08CYCLE
  HAL_SPI_MIDI_DELAY_09CYCLE
  HAL_SPI_MIDI_DELAY_10CYCLE
  HAL_SPI_MIDI_DELAY_11CYCLE
  HAL_SPI_MIDI_DELAY_12CYCLE
  HAL_SPI_MIDI_DELAY_13CYCLE
  HAL_SPI_MIDI_DELAY_14CYCLE
  HAL_SPI_MIDI_DELAY_15CYCLE
} hal_spi_midi_delay_t;

Related concepts:

HAL SPI FIFO threshold

HAL1

HAL2 



#define SPI_FIFO_THRESHOLD_01DATA
#define SPI_FIFO_THRESHOLD_02DATA
#define SPI_FIFO_THRESHOLD_03DATA
#define SPI_FIFO_THRESHOLD_04DATA
#define SPI_FIFO_THRESHOLD_05DATA
#define SPI_FIFO_THRESHOLD_06DATA
#define SPI_FIFO_THRESHOLD_07DATA
#define SPI_FIFO_THRESHOLD_08DATA
#define SPI_FIFO_THRESHOLD_09DATA
#define SPI_FIFO_THRESHOLD_10DATA
#define SPI_FIFO_THRESHOLD_11DATA
#define SPI_FIFO_THRESHOLD_12DATA
#define SPI_FIFO_THRESHOLD_13DATA
#define SPI_FIFO_THRESHOLD_14DATA
#define SPI_FIFO_THRESHOLD_15DATA
#define SPI_FIFO_THRESHOLD_16DATA

typedef enum
{
  HAL_SPI_FIFO_THRESHOLD_01DATA
  HAL_SPI_FIFO_THRESHOLD_02DATA
  HAL_SPI_FIFO_THRESHOLD_03DATA
  HAL_SPI_FIFO_THRESHOLD_04DATA
  HAL_SPI_FIFO_THRESHOLD_05DATA
  HAL_SPI_FIFO_THRESHOLD_06DATA
  HAL_SPI_FIFO_THRESHOLD_07DATA
  HAL_SPI_FIFO_THRESHOLD_08DATA
  HAL_SPI_FIFO_THRESHOLD_09DATA
  HAL_SPI_FIFO_THRESHOLD_10DATA
  HAL_SPI_FIFO_THRESHOLD_11DATA
  HAL_SPI_FIFO_THRESHOLD_12DATA
  HAL_SPI_FIFO_THRESHOLD_13DATA
  HAL_SPI_FIFO_THRESHOLD_14DATA
  HAL_SPI_FIFO_THRESHOLD_15DATA
  HAL_SPI_FIFO_THRESHOLD_16DATA
} hal_spi_fifo_threshold_t;

Related concepts:

HAL SPI mode

HAL1

HAL2 



#define SPI_MODE_SLAVE
#define SPI_MODE_MASTER

typedef enum
{
  HAL_SPI_MODE_SLAVE
  HAL_SPI_MODE_MASTER
} hal_spi_mode_t;

Related concepts:

HAL SPI direction mode

HAL1

HAL2 



#define SPI_DIRECTION_2LINES
#define SPI_DIRECTION_2LINES_TXONLY
#define SPI_DIRECTION_2LINES_RXONLY
#define SPI_DIRECTION_1LINE

typedef enum
{
  HAL_SPI_DIRECTION_FULL_DUPLEX
  HAL_SPI_DIRECTION_SIMPLEX_TX
  HAL_SPI_DIRECTION_SIMPLEX_RX
  HAL_SPI_DIRECTION_HALF_DUPLEX
} hal_spi_direction_t;

Related concepts:

HAL SPI data size

HAL1

HAL2 



#define SPI_DATASIZE_4BIT
#define SPI_DATASIZE_5BIT
#define SPI_DATASIZE_6BIT
#define SPI_DATASIZE_7BIT
#define SPI_DATASIZE_8BIT
#define SPI_DATASIZE_9BIT
#define SPI_DATASIZE_10BIT
#define SPI_DATASIZE_11BIT
#define SPI_DATASIZE_12BIT
#define SPI_DATASIZE_13BIT
#define SPI_DATASIZE_14BIT
#define SPI_DATASIZE_15BIT
#define SPI_DATASIZE_16BIT
#define SPI_DATASIZE_17BIT
#define SPI_DATASIZE_18BIT
#define SPI_DATASIZE_19BIT
#define SPI_DATASIZE_20BIT
#define SPI_DATASIZE_21BIT
#define SPI_DATASIZE_22BIT
#define SPI_DATASIZE_23BIT
#define SPI_DATASIZE_24BIT
#define SPI_DATASIZE_25BIT
#define SPI_DATASIZE_26BIT
#define SPI_DATASIZE_27BIT
#define SPI_DATASIZE_28BIT
#define SPI_DATASIZE_29BIT
#define SPI_DATASIZE_30BIT
#define SPI_DATASIZE_31BIT
#define SPI_DATASIZE_32BIT

typedef enum
{
  HAL_SPI_DATA_WIDTH_4BIT
  HAL_SPI_DATA_WIDTH_5BIT
  HAL_SPI_DATA_WIDTH_6BIT
  HAL_SPI_DATA_WIDTH_7BIT
  HAL_SPI_DATA_WIDTH_8BIT
  HAL_SPI_DATA_WIDTH_9BIT
  HAL_SPI_DATA_WIDTH_10BIT
  HAL_SPI_DATA_WIDTH_11BIT
  HAL_SPI_DATA_WIDTH_12BIT
  HAL_SPI_DATA_WIDTH_13BIT
  HAL_SPI_DATA_WIDTH_14BIT
  HAL_SPI_DATA_WIDTH_15BIT
  HAL_SPI_DATA_WIDTH_16BIT
  HAL_SPI_DATA_WIDTH_17BIT
  HAL_SPI_DATA_WIDTH_18BIT
  HAL_SPI_DATA_WIDTH_19BIT
  HAL_SPI_DATA_WIDTH_20BIT
  HAL_SPI_DATA_WIDTH_21BIT
  HAL_SPI_DATA_WIDTH_22BIT
  HAL_SPI_DATA_WIDTH_23BIT
  HAL_SPI_DATA_WIDTH_24BIT
  HAL_SPI_DATA_WIDTH_25BIT
  HAL_SPI_DATA_WIDTH_26BIT
  HAL_SPI_DATA_WIDTH_27BIT
  HAL_SPI_DATA_WIDTH_28BIT
  HAL_SPI_DATA_WIDTH_29BIT
  HAL_SPI_DATA_WIDTH_30BIT
  HAL_SPI_DATA_WIDTH_31BIT
  HAL_SPI_DATA_WIDTH_32BIT
} hal_spi_data_width_t;

Related concepts:

HAL SPI clock polarity

HAL1

HAL2 



#define SPI_POLARITY_LOW
#define SPI_POLARITY_HIGH

typedef enum
{
  HAL_SPI_CLOCK_POLARITY_LOW
  HAL_SPI_CLOCK_POLARITY_HIGH
} hal_spi_clock_polarity_t;

Related concepts:

HAL SPI clock phase

HAL1

HAL2 



#define SPI_PHASE_1EDGE
#define SPI_PHASE_2EDGE

typedef enum
{
  HAL_SPI_CLOCK_PHASE_1EDGE
  HAL_SPI_CLOCK_PHASE_2EDGE
} hal_spi_clock_phase_t;

Related concepts:

HAL SPI slave select management

HAL1

HAL2 



#define SPI_NSS_SOFT
#define SPI_NSS_HARD_INPUT
#define SPI_NSS_HARD_OUTPUT

typedef enum
{
  HAL_SPI_NSS_PIN_MGMT_INTERNAL
  HAL_SPI_NSS_PIN_MGMT_INPUT
  HAL_SPI_NSS_PIN_MGMT_OUTPUT
} hal_spi_nss_pin_management_t;

Related concepts:

HAL SPI NSS pulse mode

HAL1

HAL2 



#define SPI_NSS_PULSE_DISABLE
#define SPI_NSS_PULSE_ENABLE

typedef enum
{
  HAL_SPI_NSS_PULSE_DISABLE
  HAL_SPI_NSS_PULSE_ENABLE
} hal_spi_nss_pulse_t;

Related concepts:

HAL SPI baudrate prescaler

HAL1

HAL2 



#define SPI_BAUDRATEPRESCALER_BYPASS
#define SPI_BAUDRATEPRESCALER_2
#define SPI_BAUDRATEPRESCALER_4
#define SPI_BAUDRATEPRESCALER_8
#define SPI_BAUDRATEPRESCALER_16
#define SPI_BAUDRATEPRESCALER_32
#define SPI_BAUDRATEPRESCALER_64
#define SPI_BAUDRATEPRESCALER_128
#define SPI_BAUDRATEPRESCALER_256

typedef enum
{
  HAL_SPI_BAUDRATE_PRESCALER_BYPASS
  HAL_SPI_BAUDRATE_PRESCALER_2
  HAL_SPI_BAUDRATE_PRESCALER_4
  HAL_SPI_BAUDRATE_PRESCALER_8
  HAL_SPI_BAUDRATE_PRESCALER_16
  HAL_SPI_BAUDRATE_PRESCALER_32
  HAL_SPI_BAUDRATE_PRESCALER_64
  HAL_SPI_BAUDRATE_PRESCALER_128
  HAL_SPI_BAUDRATE_PRESCALER_256
} hal_spi_baudrate_prescaler_t;

Related concepts:

HAL SPI MSB LSB transmission

HAL1

HAL2 



#define SPI_FIRSTBIT_MSB
#define SPI_FIRSTBIT_LSB

typedef enum
{
  HAL_SPI_MSB_FIRST
  HAL_SPI_LSB_FIRST
} hal_spi_first_bit_t;

Related concepts:

HAL SPI TI mode

HAL1

HAL2 


#define SPI_TIMODE_DISABLE
#define SPI_TIMODE_ENABLE

Removed; use the following APIs instead. 

hal_status_t HAL_SPI_DisableTIMode(hal_spi_handle_t *hspi) and
hal_status_t HAL_SPI_EnableTIMode(hal_spi_handle_t *hspi) instead.

HAL SPI CRC calculation

HAL1

HAL2 


#define SPI_CRCCALCULATION_DISABLE
#define SPI_CRCCALCULATION_ENABLE

Removed; use the following APIs instead. 

hal_status_t HAL_SPI_EnableCRC(hal_spi_handle_t *hspi) and
hal_status_t HAL_SPI_DisableCRC(hal_spi_handle_t *hspi) instead.

HAL SPI CRC length

HAL1

HAL2 



#define SPI_CRC_LENGTH_DATASIZE
#define SPI_CRC_LENGTH_4BIT
#define SPI_CRC_LENGTH_5BIT
#define SPI_CRC_LENGTH_6BIT
#define SPI_CRC_LENGTH_7BIT
#define SPI_CRC_LENGTH_8BIT
#define SPI_CRC_LENGTH_9BIT
#define SPI_CRC_LENGTH_10BIT
#define SPI_CRC_LENGTH_11BIT
#define SPI_CRC_LENGTH_12BIT
#define SPI_CRC_LENGTH_13BIT
#define SPI_CRC_LENGTH_14BIT
#define SPI_CRC_LENGTH_15BIT
#define SPI_CRC_LENGTH_16BIT
#define SPI_CRC_LENGTH_17BIT
#define SPI_CRC_LENGTH_18BIT
#define SPI_CRC_LENGTH_19BIT
#define SPI_CRC_LENGTH_20BIT
#define SPI_CRC_LENGTH_21BIT
#define SPI_CRC_LENGTH_22BIT
#define SPI_CRC_LENGTH_23BIT
#define SPI_CRC_LENGTH_24BIT
#define SPI_CRC_LENGTH_25BIT
#define SPI_CRC_LENGTH_26BIT
#define SPI_CRC_LENGTH_27BIT
#define SPI_CRC_LENGTH_28BIT
#define SPI_CRC_LENGTH_29BIT
#define SPI_CRC_LENGTH_30BIT
#define SPI_CRC_LENGTH_31BIT
#define SPI_CRC_LENGTH_32BIT

typedef enum
{
  HAL_SPI_CRC_LENGTH_DATASIZE
  HAL_SPI_CRC_LENGTH_4BIT
  HAL_SPI_CRC_LENGTH_5BIT
  HAL_SPI_CRC_LENGTH_6BIT
  HAL_SPI_CRC_LENGTH_7BIT
  HAL_SPI_CRC_LENGTH_8BIT
  HAL_SPI_CRC_LENGTH_9BIT
  HAL_SPI_CRC_LENGTH_10BIT
  HAL_SPI_CRC_LENGTH_11BIT
  HAL_SPI_CRC_LENGTH_12BIT
  HAL_SPI_CRC_LENGTH_13BIT
  HAL_SPI_CRC_LENGTH_14BIT
  HAL_SPI_CRC_LENGTH_15BIT
  HAL_SPI_CRC_LENGTH_16BIT
  HAL_SPI_CRC_LENGTH_17BIT
  HAL_SPI_CRC_LENGTH_18BIT
  HAL_SPI_CRC_LENGTH_19BIT
  HAL_SPI_CRC_LENGTH_20BIT
  HAL_SPI_CRC_LENGTH_21BIT
  HAL_SPI_CRC_LENGTH_22BIT
  HAL_SPI_CRC_LENGTH_23BIT
  HAL_SPI_CRC_LENGTH_24BIT
  HAL_SPI_CRC_LENGTH_25BIT
  HAL_SPI_CRC_LENGTH_26BIT
  HAL_SPI_CRC_LENGTH_27BIT
  HAL_SPI_CRC_LENGTH_28BIT
  HAL_SPI_CRC_LENGTH_29BIT
  HAL_SPI_CRC_LENGTH_30BIT
  HAL_SPI_CRC_LENGTH_31BIT
  HAL_SPI_CRC_LENGTH_32BIT
} hal_spi_crc_length_t;

Related concepts:

HAL SPI CRC calculation initialization pattern

HAL1

HAL2 



#define SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN
#define SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN

typedef enum
{
  HAL_SPI_CRC_TX_INIT_PATTERN_ALL_ZERO
  HAL_SPI_CRC_TX_INIT_PATTERN_ALL_ONE
} hal_spi_crc_tx_init_pattern_t;

Related concepts:

HAL SPI NSS polarity

HAL1

HAL2 



#define SPI_NSS_POLARITY_LOW
#define SPI_NSS_POLARITY_HIGH

typedef enum
{
  HAL_SPI_NSS_POLARITY_LOW,
  HAL_SPI_NSS_POLARITY_HIGH
} hal_spi_nss_polarity_t;

Related concepts:

HAL SPI master keep IO state

HAL1

HAL2 


#define SPI_MASTER_KEEP_IO_STATE_DISABLE
#define SPI_MASTER_KEEP_IO_STATE_ENABLE

Removed; use the following API instead 

hal_status_t HAL_SPI_MASTER_EnableKeepIOState(hal_spi_handle_t *hspi)
hal_status_t HAL_SPI_MASTER_DisableKeepIOState(hal_spi_handle_t *hspi)

HAL SPI IO swap control

HAL1

HAL2 


#define SPI_IO_SWAP_DISABLE
#define SPI_IO_SWAP_ENABLE

Removed; use the following API instead. 

hal_status_t HAL_SPI_EnableIOSwap(hal_spi_handle_t *hspi) and
hal_status_t HAL_SPI_DisableIOSwap(hal_spi_handle_t *hspi) instead.

HAL SPI master receiver auto suspend

HAL1

HAL2 


#define SPI_MASTER_RX_AUTOSUSP_DISABLE
#define SPI_MASTER_RX_AUTOSUSP_ENABLE

Removed; use the following APIs instead 

HAL_SPI_EnableMasterReceiverAutoSusp(hal_spi_handle_t *hspi)
HAL_SPI_DisableMasterReceiverAutoSusp(hal_spi_handle_t *hspi)

HAL SPI underrun behavior

HAL1

HAL2 



#define SPI_UNDERRUN_BEHAV_REGISTER_PATTERN
#define SPI_UNDERRUN_BEHAV_LAST_RECEIVED
#define SPI_UNDERRUN_BEHAV_LAST_TRANSMITTED

typedef enum
{
  HAL_SPI_UNDERRUN_BEHAV_REGISTER_PATTERN
  HAL_SPI_UNDERRUN_BEHAV_LAST_RECEIVED
} hal_spi_underrun_behavior_t;

Related concepts:

HAL SPI RDY signal input/output polarity

HAL1

HAL2 



#define SPI_RDY_POLARITY_HIGH
#define SPI_RDY_POLARITY_LOW

typedef enum
{
  HAL_SPI_READY_PIN_POLARITY_HIGH,
  HAL_SPI_READY_PIN_POLARITY_LOW
} hal_spi_ready_pin_polarity_t;

Related concepts:

HAL SPI error codes

HAL1

HAL2 

#define HAL_SPI_ERROR_NONE
#define HAL_SPI_ERROR_MODF
#define HAL_SPI_ERROR_CRC
#define HAL_SPI_ERROR_OVR
#define HAL_SPI_ERROR_FRE
#define HAL_SPI_ERROR_DMA
#define HAL_SPI_ERROR_ABORT
#define HAL_SPI_ERROR_UDR
#define HAL_SPI_ERROR_RELOAD
#define HAL_SPI_ERROR_FLAG
#define HAL_SPI_ERROR_TIMEOUT
#define HAL_SPI_ERROR_UNKNOW
#define HAL_SPI_ERROR_NOT_SUPPORTED
#define HAL_SPI_ERROR_INVALID_CALLBACK

#define HAL_SPI_ERROR_NONE
#define HAL_SPI_ERROR_MODF
#define HAL_SPI_ERROR_CRC
#define HAL_SPI_ERROR_OVR
#define HAL_SPI_ERROR_FRE
#define HAL_SPI_ERROR_DMA
#define HAL_SPI_ERROR_ABORT
#define HAL_SPI_ERROR_UDR
#define HAL_SPI_ERROR_RELOAD





#define HAL_SPI_ERROR_IO_LOCKED
#define HAL_SPI_ERROR_CREATE_MUTEX

Related concept :

HAL SPI RDY signal input master management

HAL1

HAL2 


#define SPI_RDY_MASTER_MANAGEMENT_INTERNALLY
#define SPI_RDY_MASTER_MANAGEMENT_EXTERNALLY

Removed; use the following APIs instead. 

HAL_SPI_EnableReadyPin(hal_spi_handle_t *hspi)
HAL_SPI_DisableReadyPin(hal_spi_handle_t *hspi)

HAL SPI interrupt

HAL1

HAL2 

#define SPI_IT_RXP
#define SPI_IT_TXP
#define SPI_IT_DXP
#define SPI_IT_EOT
#define SPI_IT_TXTF
#define SPI_IT_UDR
#define SPI_IT_OVR
#define SPI_IT_CRCERR
#define SPI_IT_FRE
#define SPI_IT_MODF
#define SPI_IT_ERR

  • In HAL1, those defines have been used by the __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) and __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) macros

  • In HAL2, the IT defines and macros have been removed, use LL_SPI_IsEnabledIT() instead .

    For more details, refer to: Refer to exported IT macro

HAL SPI flags definition

HAL1

HAL2 

#define SPI_FLAG_RXP
#define SPI_FLAG_TXP
#define SPI_FLAG_DXP
#define SPI_FLAG_EOT
#define SPI_FLAG_TXTF
#define SPI_FLAG_UDR
#define SPI_FLAG_OVR
#define SPI_FLAG_CRCERR
#define SPI_FLAG_FRE
#define SPI_FLAG_MODF
#define SPI_FLAG_SUSP
#define SPI_FLAG_TXC
#define SPI_FLAG_FRLVL
#define SPI_FLAG_RXWNE
#define SPI_FLAG_RXNE
#define SPI_FLAG_TXE
#define SPI_FLAG_BSY
#define SPI_FLAG_FTLVL
#define SPI_FLAG_MASK

  • In HAL1, those defines have been used by the __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) macro.

  • In HAL2, these defines and macros have been removed, use LL_SPI_IsActiveFlag() instead with the appropriate parameters.

    For more details, refer to: Check the specified SPI flag

HAL SPI reception FIFO status level

HAL1

HAL2 

#define SPI_RX_FIFO_0PACKET
#define SPI_RX_FIFO_1PACKET
#define SPI_RX_FIFO_2PACKET
#define SPI_RX_FIFO_3PACKET

Moved to the .c file as it is not intended to be used by the user.

HAL SPI autonomous mode state

HAL1

HAL2 


#define SPI_AUTO_MODE_DISABLE
#define SPI_AUTO_MODE_ENABLE

Removed; use the following API instead. 

HAL_SPI_AM_IsEnabledTrigger(const hal_spi_handle_t *hspi)

HAL SPI autonomous mode trigger selection

HAL1

HAL2 



#define SPI_GRP1_GPDMA_CH0_TCF_TRG
#define SPI_GRP1_GPDMA_CH1_TCF_TRG
#define SPI_GRP1_GPDMA_CH2_TCF_TRG
#define SPI_GRP1_GPDMA_CH3_TCF_TRG
#define SPI_GRP1_EXTI4_TRG
#define SPI_GRP1_EXTI9_TRG
#define SPI_GRP1_LPTIM1_CH1_TRG
#define SPI_GRP1_LPTIM2_CH1_TRG
#define SPI_GRP1_COMP1_TRG
#define SPI_GRP1_COMP2_TRG
#define SPI_GRP1_RTC_ALRA_TRG
#define SPI_GRP1_RTC_WUT_TRG
#define SPI_GRP2_LPDMA_CH0_TCF_TRG
#define SPI_GRP2_LPDMA_CH1_TCF_TRG
#define SPI_GRP2_LPDMA_CH2_TCF_TRG
#define SPI_GRP2_LPDMA_CH3_TCF_TRG
#define SPI_GRP2_EXTI4_TRG
#define SPI_GRP2_EXTI8_TRG
#define SPI_GRP2_LPTIM1_CH1_TRG
#define SPI_GRP2_LPTIM3_CH1_TRG
#define SPI_GRP2_COMP1_TRG
#define SPI_GRP2_COMP2_TRG
#define SPI_GRP2_RTC_ALRA_TRG
#define SPI_GRP2_RTC_WUT_TRG

typedef enum
{
  HAL_SPI_AM_TRIG_GRP1_GPDMA1_CH0_TC,
  HAL_SPI_AM_TRIG_GRP1_GPDMA1_CH1_TC,
  HAL_SPI_AM_TRIG_GRP1_GPDMA1_CH2_TC,
  HAL_SPI_AM_TRIG_GRP1_GPDMA1_CH3_TC,
  HAL_SPI_AM_TRIG_GRP1_EXTI4,
  HAL_SPI_AM_TRIG_GRP1_EXTI9,
  HAL_SPI_AM_TRIG_GRP1_LPTIM1_CH1,
  HAL_SPI_AM_TRIG_GRP1_LPTIM2_CH1,
  HAL_SPI_AM_TRIG_GRP1_COMP1_OUT,
  HAL_SPI_AM_TRIG_GRP1_COMP2_OUT,
  HAL_SPI_AM_TRIG_GRP1_RTC_ALRA_TRG,
  HAL_SPI_AM_TRIG_GRP1_RTC_WUT_TRG,
  HAL_SPI_AM_TRIG_GRP2_LPDMA1_CH0_TC,
  HAL_SPI_AM_TRIG_GRP2_LPDMA1_CH1_TC,
  HAL_SPI_AM_TRIG_GRP2_LPDMA1_CH2_TC,
  HAL_SPI_AM_TRIG_GRP2_LPDMA1_CH3_TC,
  HAL_SPI_AM_TRIG_GRP2_EXTI4,
  HAL_SPI_AM_TRIG_GRP2_EXTI8,
  HAL_SPI_AM_TRIG_GRP2_LPTIM1_CH1,
  HAL_SPI_AM_TRIG_GRP2_LPTIM3_CH1,
  HAL_SPI_AM_TRIG_GRP2_COMP1_OUT,
  HAL_SPI_AM_TRIG_GRP2_COMP2_OUT,
  HAL_SPI_AM_TRIG_GRP2_RTC_ALRA_TRG,
  HAL_SPI_AM_TRIG_GRP2_RTC_WUT_TRG
} hal_spi_am_trig_source_t;

HAL SPI autonomous mode trigger polarity

HAL1

HAL2 



#define SPI_TRIG_POLARITY_RISING
#define SPI_TRIG_POLARITY_FALLING

typedef enum
{
  HAL_SPI_AM_TRIG_RISING
  HAL_SPI_AM_TRIG_FALLING
} hal_spi_am_trig_polarity_t

HAL SPI autonomous mode trigger group

HAL1

HAL2 

#define SPI_TRIG_GRP1
#define SPI_TRIG_GRP2

#define LL_SPI_TRIG_GRP1
#define LL_SPI_TRIG_GRP2

HAL SPI underrun detection

HAL1

HAL2 

#define SPI_UNDERRUN_DETECT_BEGIN_DATA_FRAME
#define SPI_UNDERRUN_DETECT_END_DATA_FRAME
#define SPI_UNDERRUN_DETECT_BEGIN_ACTIVE_NSS

typedef struct
{
  hal_spi_underrun_behavior_t underrun_behavior;
} hal_spi_underrun_config_t;

typedef enum
{
  HAL_SPI_UNDERRUN_BEHAV_REGISTER_PATTERN,
  HAL_SPI_UNDERRUN_BEHAV_LAST_RECEIVED
} hal_spi_underrun_behavior_t;

HAL SPI transmission FIFO status level (*)

HAL1

HAL2 

#define SPI_FTLVL_EMPTY
#define SPI_FTLVL_QUARTER_FULL
#define SPI_FTLVL_HALF_FULL
#define SPI_FTLVL_FULL

Not yet implemented in HAL2.

HAL SPI reception FIFO status level (*)

HAL1

HAL2 

#define SPI_FRLVL_EMPTY
#define SPI_FRLVL_QUARTER_FULL
#define SPI_FRLVL_HALF_FULL
#define SPI_FRLVL_FULL

Not yet implemented in HAL2.

HAL SPI FIFO reception threshold (*)

HAL1

HAL2 

#define SPI_RXFIFO_THRESHOLD
#define SPI_RXFIFO_THRESHOLD_QF
#define SPI_RXFIFO_THRESHOLD_HF

Not yet implemented in HAL2.

HAL SPI FIFO type (*)

HAL1

HAL2 

#define SPI_LOWEND_FIFO_SIZE
#define SPI_HIGHEND_FIFO_SIZE

Not yet implemented in HAL2.

Note

(*) : available only for some series